The worlds of networking and FPGA design have become increasingly intertwined. Modern FPGAs are now powering everything from high-speed network interfaces to complex packet processing pipelines and industrial automation systems. Whether you’re implementing a custom Ethernet MAC, building a network security appliance, or developing a specialized network function, your FPGA design needs thorough testing and verification.
Ostinato can help you with that.
No need for expensive and complex test equipment. A simple PC and a network interface card (NIC) is all you need to run Ostinato and test your FPGA design.
Let’s explore how Ostinato can be used across different aspects of FPGA development.
Network Interface Testing
At the heart of many FPGA designs is the network interface. Whether you’re implementing a standard Ethernet MAC or a custom network interface, you need to verify its functionality under various conditions. Ostinato’s ability to generate traffic patterns (valid and invalid) at various rates including line rate makes it ideal for this purpose.
You can use Ostinato to test your FPGA’s network interface by
- Creating specific packet patterns to test basic functionality
- Generating traffic at different rates to verify performance
- Testing error handling with malformed packets
- Verifying flow control mechanisms
The Stream Configuration, Port Configuration and Port Statistics features are particularly useful here, allowing you to create specific packet patterns, monitor interface performance and identify potential issues.
Protocol Implementation Verification
When implementing network protocols in FPGAs, it’s essential to ensure they handle all protocol requirements and edge cases correctly.
You can use Ostinato to verify your FPGA’s protocol implementation by
- Testing support for various network protocols to ensure compatibility and correct processing
- Verifying protocol conformance using standard test patterns to ensure the FPGA processes packets as expected
- Injecting errors into packet streams to test the FPGA’s error handling capabilities
- Validating protocol timing requirements by measuring the timing of packet processing and ensuring it meets specifications
Ostinato’s Stream Configuration allows you to craft protocol packets as per your specific requirements. You can also use the Ostinato Hexdump and userscript features to add support for custom or unimplemented protocols.
You can also import, edit and replay PCAP files.
Please note that Ostinato is stateless and does not support stateful protocols yet.
Performance Analysis
FPGA designs often need to meet strict performance requirements. Ostinato helps you measure and analyze:
- Throughput at different packet sizes
- Latency under various load conditions
- Jitter in packet processing
- Resource utilization impact
For line rate support, you can use the Turbo Transmit add-on and run standard RFC 2544 tests using the Performance Benchmark automated test suite.
Security Testing
For FPGAs implementing security functions, Ostinato can help verify:
- Firewall rule implementations
- DDoS protection mechanisms
- Security protocol handling
Test Automation
Modern FPGA development requires automated testing. Ostinato’s Python API allows you to do all that you can using the Ostinato GUI and more that is not possible using the GUI.
- Create automated test scenarios
- Integrate with your verification environment
- Generate test reports
- Perform regression testing
Use with Emulated Designs
Ostinato can integrate with FPGA/ASIC designs running on emulation via a speedbridge. This integration allows for comprehensive testing and verification of your design in a controlled environment before deploying it on actual hardware.
- Detect issues early in the development cycle, reducing the risk of costly errors later on
- Enjoy a flexible testing environment where you can easily modify and test different configurations and scenarios without the need for physical hardware changes
- Use Ostinato to generate and send traffic to the emulated design, configuring specific traffic patterns, rates, and protocols to match your testing requirements
- Ensure your design correctly implements and handles various network protocols by simulating different protocol scenarios
By leveraging Ostinato in an emulated environment, you can enhance the reliability and performance of your FPGA/ASIC designs, ensuring they are ready for deployment in real-world applications.
Troubleshooting
- Craft specific test patterns to reproduce issues
- Replay known-to-cause-problem PCAP files to help identify and fix issues with your FPGA design
Case Studies
Here are some publicly available case studies that have used Ostinato for their FPGA development and troubleshooting.
- Increasing PTP accuracy and resiliency
- Analysing full duplex capture in Industrial Ethernet
- Packets of Death for an Ethernet Controller
Want to discuss how Ostinato can help your FPGA/ASIC development? Reach out to us!